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ASSIGNMENT
PROGRAM - MCA (REVISED
FALL 2012)
SEMESTER - SECOND
SUBJECT CODE
& NAME – BIT204- COMPUTER ARCHITECTURE
CREDIT 4, BK ID - B1648, MAX. MARKS 60
Set 1
Q1. Explain the concept of branch handling.
What is delayed branching? 5+5= 10
Answer:
Branch Handling
Branch is a flow
altering instruction that is required to be handled in a special manner in
pipelined processors. Branch instruction’s impact on the pipeline is shown in
figure as
Q2. Explain any five types of vector
instructions in detail.5*2= 10
Answer: Types of Vector Instructions:
(a) Vector-scalar instructions: Using these instructions, a
scalar operand can be combined with a vector one. If A and B are vector
registers and f is a function that performs some operation
Q3. Write short notes on:
a) UMA
b) NUMA 5+5= 10
Answer:
a)
UMA
(Uniform Memory Access):
In this category every processor
and memory module has similar access time. Hence each memory word can be read
as quickly as other memory word. If not then quick references are slowed down
to match the slow ones, so that programmers cannot find the difference this is
Set 2
Q1. Differentiate between Process and Thread.
5+5=10
Answer:
Concept of process
In operating system terminology,
instead of the term ‘program’, the notion of process is used in connection with
execution. It designates a commission or job, or a quantum of work dealt with
as an entity. Consequently, the resources required, such as address space, are
typically allocated
Q2. Explain the any five types of
addressing modes. 5*2= 10
Answer:
Every instruction of a computer
states an operation on certain data. There are a numerous ways of specifying
address of the data to be operated on. These different ways of specifying data
are called the addressing modes In addition to stating registers and constant
operands,
Q3. Describe the logical layout of both
RISC and CISC computers 5+5= 10
Answer:
While processing operates
instructions, RISC pipelines have to cope only with register operands. By
contrast, CISC pipelines must be able to deal with both register and memory
operands as well as destinations.
Pipeline in RISC architecture: Before discussing pipelines in
RISC machines, let us first discuss what is
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